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Like pretty much all computer systems, the 6502-based Commodore PET/CBM series can be reset to a defined state via an electrical pulse. On the 6502, this is achieved by applying a LOW signal to the processor's /RESET input (pin 40); when the input voltage returns to HIGH, the CPU begins executing the program code located at the address stored in the so-called reset vector at $FFFC/$FFFD. In the PET, for instance, this process initializes the I/O chips (PIA and VIAs) -- which handle tasks such as keyboard scanning and the IEC bus -- performs a memory test, and displays the startup message before entering the BASIC input loop.

And it is precisely this memory test that can pose a problem.

This happens, for example, if you have managed to crash the computer -- perhaps due to an ill-advised POKE command -- after a long, painstaking programming session.

If you then use a standard reset button, the RAM gets overwritten during the test, and that’s the end of your BASIC code.

Fortunately, there is a solution. One of the I/O lines (PA7) on the PIA chip (6520) is routed to pin 5 of the user port (designated as /DIAG). This line is checked very early in the reset routine; if a LOW level is detected, the system branches to an alternative, abbreviated startup routine that skips the memory test. (It ends with a BRK command, landing you in the machine language monitor-- which can simply be exited by pressing [X].)

The now is: how can one apply a LOW level to the /DIAG line when needed?

Reset button "deluxe"

My goal was a circuit that pulls the /DIAG line LOW briefly when a reset button is pressed; this way, a short press triggers the alternative reset routine (skipping the memory test), whereas a longer press allows /DIAG to return to HIGH, resulting in a standard reset.

After several unsuccessful attempts to implement the design using only passive components (resistors, capacitors, diodes), I finally had to opt for a 555 timer in monostable mode to generate the short LOW pulse. However, since the 555 initially outputs a HIGH pulse, a transistor was required to act as an inverter. The resulting circuit diagram looks like this:

How does it work?

  • R1 acts as a pull-up resistor, holding /RESET HIGH by default.
  • Closing SW1 pulls /RESET LOW, which also triggers the 555 timer.
  • R4 and C2 determine the duration of the emitted HIGH pulse.
  • /DIAG is normally held HIGH by pull-up resistor R5.
  • The HIGH pulse from the 555 switches on transistor Q1 via R4, pulling /DIAG LOW.
  • At the end of the pulse, the transistor switches off, and /DIAG returns to HIGH.
  • Depending on how long SW1 is held down, /DIAG will either still be LOW (short press) or already HIGH (long press), resulting in the execution of one reset variant or the other.
  • C3 helps smooth out fluctuations in the control signal for the 555's internal reference voltage (not actually used, since tied to GND).
  • Finally, R2 and C1 form a reset circuit for the 555 itself; upon power-up, they briefly pull its THRES input LOW.

Wiring

Inside the PET, various lines are tapped from suitable solder points on the cassette interface (Pin 1: GND; Pin 2: +5 V) and the user port (Pin 5: /DIAG). The /RESET signal is not connected directly to the system bus's /RESET line; instead, it connects to the trigger pin (Pin 2) of the 555 chip (A2) on the PET motherboard, which is used internally to generate the reset pulse when the computer is powered on. The circuit itself was built on a small piece of stripboard and attached to the back of the PET's case with a dab of hot glue, right next to the hole for the push-button.

What's next?

A few ideas for further development:

  • A potentiometer instead of fixed resistor R3 for fine-tuning the /DIAG pulse duration
  • An option to swap the functions of short and long button presses, so that a short press performs a normal reset while a long press performs the memory-preserving one
  • Finally learning PCB layout and making (or having made) a proper PCB instead of messing around with stripboard...